C8051F970-A-GM Datasheet, PDF (377/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 30.4. I2C0STAT: I2C0 Status
Bit
7
6
5
4
3
2
1
0
Name HSMODE ACTIVE I2C0INT NACK
START
STOP
WR
RD
Type
R
R
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0xF8 (bit-addressable)
Bit
Name
Function
7
HSMODE High Speed Mode.
This bit is set to 1 by hardware when a High Speed master code is received received and
automatically clears when a STOP event occurs.
6
ACTIVE Bus Active.
This bit is set to 1 by hardware when an incoming slave address matches and automati-
cally clears when the transfer completes with either a STOP or a NACK event.
5
I2C0INT I2C Interrupt.
This bit is set when a read (RD), write (WR), or a STOP event (STOP) occurs. This bit
will also set when the ACTIVE bit goes low to indicate the end of a transfer. This bit will
generate an interrupt, and hardware will automatically clear this bit after the RD and WR
bits clear.
4
NACK NACK.
This bit is set by hardware when one of the following conditions are met:
- A NACK is transmitted by either a Master or a Slave when the ACTIVE bit is high.
- An I2C slave transmits a NACK to a matching slave address.
Hardware will automatically clear this bit.
3
START Start.
This bit is set by hardware when a START is received and a matching slave address is
received. Hardware will automatically clear this bit.
2
STOP Stop.
This bit is set by hardware when a STOP is received and the last slave address received
matches the value in the I2C0SLAD register. Hardware will automatically clear this bit.
1
WR
I2C Write.
This bit is set by hardware on the 9th SCL falling edge when one of the following condi-
tions are met:
- The I2C0 Slave responds with an ACK, and the DMA has not enabled I2C Write as a
data transfer function.
- The I2C0 Slave responds with a NACK, and the DMA has not enabled I2C Write as a
data transfer function.
- The current byte transaction has a matching I2C0 Slave address and the 8th bit was a
WRITE bit (0).
This bit will set the I2C0INT bit and generate an interrupt, if enabled. Hardware will auto-
matically clear this bit.
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Rev 1.0