C8051F970-A-GM Datasheet, PDF (277/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
26. Port I/O (Port 0, Port 1, Port 2, Port 3, Port 4, Port 5, Port 6, Crossbar,
and Port Match)
Digital and analog resources on the C8051F97x family are externally available on the device’s multi-purpose I/O
pins. Port pins P0.0-P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital
resources through the crossbar, or assigned to an analog function. Port pins P3.0-P6.1 can be used as GPIO. Port
pin P5.2 is shared with the C2 Interface Data signal (C2D). The designer has complete control over which functions
are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a priority crossbar decoder. Note that the state of a port I/O pin can always be read in the
corresponding port latch, regardless of the crossbar settings.
The crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 26.2 and Figure 26.3). The registers XBR0 and XBR1 are used to select internal digital functions.
The port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT,
where n = 0,1). Additionally, each bank of port pins (P0, P1, P2, P3, P4, and P5) have two selectable drive strength
settings. The P6 pins only support digital open-drain mode and cannot be configured as digital push-pull pins.
2
SMBus0
4
SPI0
2
UART0
1
SYSCLK
3
PCA (CEXn)
1
PCA (ECI)
1
Timer 0
1
Timer 1
Priority Crossbar
Decoder
Port Match
INT0 / INT1
ADC0 In
CS0 In
I2C0 Slave In / Out
Port 0
Control &
Config
Port 1
Control &
Config
Port 2
Control &
Config
Port 3
Control &
Config
Port 4
Control &
Config
Port 5
Control &
Config
Port 6
Control &
Config
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
P5.0
P5.1
P5.2
P6.0
P6.1
Figure 26.1. Port I/O Functional Block Diagram
278
Rev 1.0