C8051F970-A-GM Datasheet, PDF (188/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
21.1. DMA0 Architecture
The first step in configuring a DMA0 channel is to select the desired channel for data transfer using DMA0SEL[2:0]
bits (DMA0SEL). After setting the DMA0 channel, firmware can address channel-specific registers such as
DMA0NCF, DMA0NBAH/L, DMA0NAOH/L, and DMA0NSZH/L. Once firmware selects a channel, the subsequent
SFR configuration applies to the DMA0 transfer of that selected channel.
Each DMA0 channel consists of an SFR assigning the channel to a peripheral, a channel control register and a set
of SFRs that describe XRAM and SFR addresses to be used during data transfer (Figure 21.1). The peripheral
assignment bits of DMA0nCF select one of the eight data transfer functions. The selected channel can choose the
desired function by writing to the PERIPH field in the DMA0NCF register.
The control register DMA0NCF of each channel configures the endianness of the data in XRAM, stall enable, full-
length interrupt enable and mid-point interrupt enable. When a channel is stalled by setting the STALL bit
(DMA0NCF.5), DMA0 transfers in progress will not be aborted, but new DMA0 transfers will be blocked until the
stall status of the channel is reset. After the stall bit is set, software should poll the corresponding CHnBUSY bit to
verify that there are no more DMA transfers for that channel.
The memory interface configuration SFRs of a channel define the linear region of XRAM involved in the transfer
through a 12-bit base address register DMA0NBAH:L, a 10-bit address offset register DMA0NAOH/L and a 10-bit
data transfer size DMA0NSZH:L. The effective memory address is the address involved in the current DMA0
transaction.
Effective Memory Address = Base Address + Address Offset
The address offset serves as byte counter. The address offset should be always less than data transfer length. The
address offset increments by one after each byte transferred. For DMA0 configuration of any channel, address
offsets of active channels should be reset to 0 before DMA0 transfers occur.
Data transfer size DMA0NSZH:L defines the maximum number of bytes for the DMA0 transfer of the selected
channel. If the address offset reaches data transfer size, the full-length interrupt flag bit CHnI (DMA0INT) of the
selected channel will be asserted. Similarly, the mid-point interrupt flag bit CHnMI is set when the address offset is
equal to half of data transfer size if the transfer size is an even number or when the address offset is equal to half
of the transfer size plus one if the transfer size is an odd number. Interrupt flags must be cleared by software so
that the next DMA0 data transfer can proceed.
The DMA0 subsystem permits data transfer between SFR registers and XRAM. The DMA0 subsystem executes its
task based on settings of a channel’s control and memory interface configuration SFRs. When data is copied from
XRAM to SFR registers, it takes two cycles for DMA0 to read from XRAM and the SFR write occurs in the second
cycle. If more than one byte is involved, a pipeline is used. When data is copied from SFR registers to XRAM, the
DMA0 only requires one cycle for one byte transaction.
The selected DMA0 channel for a peripheral should be enabled through the enable bits CHnEN (DMA0EN.n) to
allow the DMA0 to transfer the data. When the DMA0 is transferring data on a channel, the busy status bit of the
channel CHnBUSY (DMA0BUSY.n) is set. During the transaction, writes to DMA0NSZH:L, DMA0NBAH:L, and
DMA0NAOH:L are disabled.
Besides reporting transaction status of a channel, DMA0BUSY can be used to force a DMA0 transfer on an already
configured channel by setting the CHnBUSY bit (DMA0BUSY.n). This is useful for communication peripherals such
as the I2C0. For example, after the I2C0 acknowledges the received slave address from I2C Master during a read
transaction, a byte of data should be written to the I2C0DOUT register that will be transmitted to the I2C Master
during the next I2C data transfer. Writing 1 to the CHn_BUSY bit (DMA0BUSY.n) of an enabled DMA0 channel
forces a data transfer from the XRAM to I2C0DOUT.
21.2. DMA0 Arbitration
21.2.1. DMA0 Memory Access Arbitration
If both DMA0 and CPU attempt to access SFR register or XRAM at the same time, the CPU preempts the DMA0
module. DMA0 will be stalled until CPU completes its bus activity.
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