C8051F970-A-GM Datasheet, PDF (322/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
27. Reset Sources and Supply Monitor
Reset circuitry allows the controller to be easily placed in a predefined default condition. Upon entering this reset
state, the following events occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External port pins are placed in a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data
memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer
SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain, low-drive mode. Weak pullups are enabled
during and after the reset. For V_DD Monitor and power-on resets, the RST pin is driven low until the device exits the
reset state. Note that during a power-on event, there may be a short delay before the POR circuitry fires and the
RST pin is driven low. During that time, the RST pin will be weakly pulled to the V_DD supply pin.
On exit from the reset state, the program counter (PC) is reset, the Watchdog Timer is enabled and the system
clock defaults to the internal oscillator. Program execution begins at location 0x0000.
RST
Supply Monitor or
Power-up
Missing Clock
Detector
Watchdog Timer
Software Reset
SmaRTClock
Alarm/Error
Flash Error
Reset Sources
system reset
Figure 27.1. Reset Sources
Rev 1.0
323