C8051F970-A-GM Datasheet, PDF (215/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 22.2. MAC0CF0: MAC0 Configuration 0
Bit
7
6
5
4
Name SHIFTEN SHIFTDIR CLRACC FRACMD
Type
W
RW
W
RW
Reset
0
0
0
0
SFR Page = 0xF; SFR Address: 0xC0 (bit-addressable)
3
ACCMD
RW
0
2
ACCNE-
GATE
RW
0
1
0
BNEGATE ANEGATE
RW
RW
0
0
Bit
Name
Function
7
SHIFTEN Accumulator Shift Control.
When this bit is set, hardware shifts the 40-bit MAC0 accumulator by 1 bit. This bit also
enables multi-bit shifts in DMA mode.
0: Do not shift the accumulator by one bit in the SHIFTDIR direction.
1: Shift the accumulator by one bit in the SHIFTDIR direction.
6
SHIFTDIR Accumulator Shift Direction.
This bit controls the direction of the accumulator shift activated by the SHIFTEN bit.
0: The MAC0 accumulator will be shifted left.
1: The MAC0 accumulator will be shifted right.
5
CLRACC Clear Accumulator.
This bit works only in MCU mode only and is used to reset the accumulator before the
next operation. When this bit is set, the MAC0 accumulator will be cleared to zero. In
addition, all bits in the MAC0STA register except MAC0INT and ACCRDY are cleared.
Hardware will automatically clear this bit when the operation completes. Firmware will
always read this bit as 0.
4
FRACMD Fractional Mode.
0: MAC0 operates in Integer Mode.
1: MAC0 operates in Fractional Mode.
3
ACCMD Accumulate Mode.
0: Select multiply-and-accumulate (MAC) mode.
1: Select multiply-only mode.
2
ACCNE- Negate Accumulator Input.
GATE _{This bit controls whether hardware negates the accumulator before it is added with the}
multiplication result of A and B. If this bit is set to 1, the SIGNEDEN bit must also be set
to 1, enabling signed arithmetic.
0: No change is applied to the accumulator before it is added to the multiplication result
of A and B.
1: Hardware negates the accumulator before it is added to the multiplication result of A
and B.
216
Rev 1.0