C8051F970-A-GM Datasheet, PDF (363/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 29.5. SMB0DAT: SMBus 0 Data
Bit
7
6
5
4
3
2
1
0
Name
SMB0DAT
Type
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xC2
Table 29.11. SMB0DAT Register Bit Descriptions
Bit
Name
Function
7:0 SMB0DAT SMBus 0 Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial
interface or a byte that has just been received on the SMBus serial interface. The CPU
can safely read from or write to this register whenever the SI serial interrupt flag is set to
logic 1. The serial data in the register remains stable as long as the SI flag is set. When
the SI flag is not set, the system may be in the process of shifting data in/out and the
CPU should not attempt to access this register.
364
Rev 1.0