C8051F970-A-GM Datasheet, PDF (316/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 26.32. P5: Port 5 Pin Latch
Bit
7
6
5
4
Name
Reserved
Type
RW
Reset
0
0
0
0
SFR Page = 0x0; SFR Address: 0xE3
3
2
1
0
B2
B1
B0
RW
RW
RW
0
1
1
1
Table 26.35. P5 Register Bit Descriptions
Bit
Name
Function
7:3
Reserved Must write reset value.
2
B2
Port 5 Bit 2 Latch.
0: P5.2 is low. Set P5.2 to drive low.
1: P5.2 is high. Set P5.2 to drive or float high.
1
B1
Port 5 Bit 1 Latch.
0: P5.1 is low. Set P5.1 to drive low.
1: P5.1 is high. Set P5.1 to drive or float high.
0
B0
Port 5 Bit 0 Latch.
0: P5.0 is low. Set P5.0 to drive low.
1: P5.0 is high. Set P5.0 to drive or float high.
Notes:
1. Writing this register sets the port latch logic value for the associated I/O pins configured as digital I/O.
2. Reading this register returns the logic value at the pin, regardless if it is configured as output or input.
Rev 1.0
317