C8051F970-A-GM Datasheet, PDF (87/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 13.4. EIP1: Extended Interrupt Priority 1
Bit
7
6
5
4
3
2
1
Name
PT3
PDMA0 PDMA0M PPCA0 PADC0 PWADC0 PRTC0A
Type
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0xF6
Table 13.5. EIP1 Register Bit Descriptions
Bit
Name
Function
7
PT3
Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6
PDMA0 DMA0 Interrupt Priority Control.
This bit sets the priority of the DMA0 interrupt.
0: DMA0 interrupts set to low priority level.
1: DMA0 interrupts set to high priority level.
5
PDMA0M DMA0 Mid-Point Interrupt Priority Control.
This bit sets the masking of the DMA0 Mid-Point interrupt.
0: Mid-point DMA0 interrupts set to low priority level.
1: Mid-point DMA0 interrupts set to high priority level.
4
PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3
PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2
PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1
PRTC0A RTC Alarm Interrupt Priority Control.
This bit sets the priority of the RTC Alarm interrupt.
0: RTC Alarm interrupt set to low priority level.
1: RTC Alarm interrupt set to high priority level.
0
PSMB0
RW
0
Rev 1.0
87