C8051F970-A-GM Datasheet, PDF (356/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Table 29.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1)
Values Read
Values to
Write
Current SMbus State
Typical Response Options
1110 0 0 X A master START was generated.
Load slave address + R/W into _{0 0 X 1100}
SMB0DAT.
0
0
0
A master data or address byte was
transmitted; NACK received.
Set STA to restart transfer.
Abort transfer.
1 0 X 1110
01X —
Load next data byte into SMB0- _{0 0 X 1100}
DAT.
1100
0
0
1
A master data or address byte was
transmitted; ACK received.
End transfer with STOP.
01X —
End transfer with STOP and start _{1 1 X —}
another transfer.
Send repeated START.
1 0 X 1110
Switch to Master Receiver Mode _{0 0 1 1000}
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
Set ACK for next data byte;
Read SMB0DAT.
0 0 1 1000
Set NACK to indicate next data
byte as the last data byte;
0
0
1
A master data byte was received; ACK
sent.
Read SMB0DAT.
Initiate repeated START.
0 0 0 1000
1 0 0 1110
1000
Switch to Master Transmitter
0 0 X 1100
Mode (write to SMB0DAT before
clearing SI).
Read SMB0DAT; send STOP. 0 1 0 —
0
0
0
A master data byte was received;
NACK sent (last byte).
Read SMB0DAT; Send STOP
followed by START.
1 1 0 1110
Initiate repeated START.
1 0 0 1110
Switch to Master Transmitter
0 0 X 1100
Mode (write to SMB0DAT before
clearing SI).
Rev 1.0
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