C8051F970-A-GM Datasheet, PDF (25/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
2.1.2.1. Normal Mode
Normal mode encompasses the typical full-speed operation. The power consumption of the device in this mode will
vary depending on the system clock speed and any analog peripherals that are enabled.
2.1.2.2. Idle Mode
Setting the IDLE bit in PCON causes the hardware to halt the CPU and enter idle mode as soon as the instruction
that sets the bit completes execution. All internal registers and memory maintain their original data. All analog and
digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an enabled
interrupt will cause the IDLE bit to be cleared and the CPU to resume operation. The pending interrupt will be
serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction
immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external
reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000.
2.1.2.3. Stop Mode
Setting the Stop Mode Select bit in the PCON register causes the core to enter stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode, the precision internal oscillator and CPU are
stopped; the state of the low power oscillator and the external oscillator circuit is not affected. Each analog
peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop
mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset
sequence and begins program execution at address 0x0000.
2.1.3. Suspend Mode
Setting the Suspend Mode Select bit in the PMU0CF register causes the system clock to be gated off and all
internal oscillators disabled. All digital logic (timers, communication peripherals, interrupts, CPU, etc.) stops
functioning until one of the enabled wake-up sources occurs.
The following wake-up sources can be configured to wake the device from suspend mode:
SmaRTClock oscillator fail
SmaRTClock alarm
Port Match event
I2C0 address match
CS0 end-of-conversion or end-of-scan
2.1.4. Sleep Mode
Setting the Sleep Mode Select bit in the PMU0CF register turns off the internal 1.8 V regulator (VREG0) and
switches the power supply of all on-chip RAM to the VDD pin. Power to most digital logic on the chip is
disconnected; only PMU0 and the SmaRTClock remain powered. All analog peripherals (ADC0, External
Oscillator, etc.) should be disabled prior to entering sleep mode.
RAM and SFR register contents are preserved in sleep mode as long as the voltage on VDD does not fall below
VPOR. The PC counter and all other volatile state information is preserved allowing the device to resume code
execution upon waking up from sleep mode. The following wake-up sources can be configured to wake the device
from sleep mode:
SmaRTClock oscillator fail
SmaRTClock alarm
Port Match event
I2C0 address match
Rev 1.0
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