C8051F970-A-GM Datasheet, PDF (206/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
MAC0 Accumulator updated is true
when one of following conditions are
met (higher priority first):
1. ACCMD == 0
2. DMA is enabled and DMA
transferred of N bytes from XRAM;
where N = ACCDMAIN
3. DMA was not enabled – re-use
existing value in accumulator
MAC0A updated is true when one of
following conditions are met (higher
priority first):
1. APOSTINC == 1: Increments MAC0A if
true
2. ADMASRC == 1
3. DMA enabled and DMA transferred 2
bytes from XRAM to MAC0A
MAC0B updated is true when one of
following conditions are met (higher
priority first):
1. BPOSTINC == 1: Increments MAC0B if
true
2. BDMASRC == 1
3. DMA enabled and DMA transferred 2
bytes from XRAM to MAC0B
BUSY = 1
OpCtr = 0
Firmware triggers DMA-enabled
MAC operation after setting up other
MAC0 configuration bits and DMA
channels
OpCtr keeps track of number of
MAC operations before requesting
for DMA transfer from/to MAC0
Accumulator
N
MAC0 Accumulator
X
updated?
Y
N
MAC0A updated?
X
Y
N
MAC0B updated?
X
Y
MAC0 performs MAC
operation
OpCtr = OpCtr + 1
N
OpCtr=MAC0ITER?
Y
Y MAC0 Accumulator
transferred out?
N
BUSY = 0
MAC0 Accumulator transferred out
is true when DMA is enabled and
DMA transferred N bytes from
XRAM where N = ACCDMAOUT
X
Exit DMA Mode
Operation
Figure 22.4. DMA Mode Operation Flow Chart
Rev 1.0
207