C8051F970-A-GM Datasheet, PDF (182/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 20.6. PSW: Program Status Word
Bit
7
6
5
4
3
2
1
0
Name
CY
AC
F0
RS
OV
F1
PARITY
Type
RW
RW
RW
RW
RW
RW
R
Reset
0
0
0
0
0
0
0
0
SFR Page = ALL; SFR Address: 0xD0 (bit-addressable)
Table 20.7. PSW Register Bit Descriptions
Bit
Name
Function
7
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
6
AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-
metic operations.
5
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under firmware control.
4:3
RS
Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2
OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
1. An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
2. A MUL instruction results in an overflow (result is greater than 255).
3. A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1
F1
User Flag 1.
This is a bit-addressable, general purpose flag for use under firmware control.
0
PARITY Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
Rev 1.0
183