C8051F970-A-GM Datasheet, PDF (323/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
27.1. Power-On Reset
During power-up, the POR circuit will fire. When POR fires, the device is held in a reset state and the RST pin is
driven low until V_DD settles above V_RST. Two delays are present during the supply ramp time. First, a delay will
occur before the POR circuitry fires and pulls the RST pin low. A second delay occurs before the device is released
from reset; the delay decreases as the V_DD ramp time increases (V_DD ramp time is defined as how fast V_DD ramps
from 0 V to V_RST). Figure 27.2. plots the power-on reset timing. For ramp times less than 1 ms, the power-on reset
time (T_POR) is typically less than 0.3 ms. Additionally, the power supply must reach V_RST before the POR circuit will
release the device from reset.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all
of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all
resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag to
determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be
undefined after a power-on reset. The V_DD monitor is enabled following a power-on reset.
t
RST
Logic HIGH
Logic LOW
T_POR
Power-On Reset
Figure 27.2. Power-on Reset Timing
324
Rev 1.0