C8051F970-A-GM Datasheet, PDF (106/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
17.2. Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at
the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the
AD0SJST[2:0]. When the repeat count is set to 1, conversion codes are represented as 10-bit unsigned integers.
Inputs are measured from 0 to VREF x 1023/1024. Example codes are shown below for both right-justified and left-
justified data. Unused bits in the ADC0H and ADC0L registers are set to 0.
Input Voltage
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
Right-Justified ADC0H:ADC0L
(AD0SJST = 000)
0x03FF
0x0200
0x0100
0x0000
Left-Justified ADC0H:ADC0L
(AD0SJST = 100)
0xFFC0
0x8000
0x4000
0x0000
When the repeat count is greater than 1, the output conversion code represents the accumulated result of the
conversions performed and is updated after the last conversion in the series is finished. Sets of 4, 8, 16, 32, or 64
consecutive samples can be accumulated and represented in unsigned integer format. The repeat count can be
selected using the AD0RPT bits in the ADC0AC register. When a repeat count higher than 1, the ADC output must
be right-justified (AD0SJST = 0xx); unused bits in the ADC0H and ADC0L registers are set to 0. The example
below shows the right-justified result for various input voltages and repeat counts. Notice that accumulating 2ⁿ
samples is equivalent to left-shifting by n bit positions when all samples returned from the ADC have the same
value.
Input Voltage
V_REF x 1023/1024
V_REF x 512/1024
V_REF x 511/1024
0
Repeat Count = 4
0x0FFC
0x0800
0x07FC
0x0000
Repeat Count = 16
0x3FF0
0x2000
0x1FF0
0x0000
Repeat Count = 64
0xFFC0
0x8000
0x7FC0
0x0000
The AD0SJST bits can be used to format the contents of the 16-bit accumulator. The accumulated result can be
shifted right by 1, 2, or 3 bit positions. Based on the principles of oversampling and averaging, the effective ADC
resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4. The example below
shows how to increase the effective ADC resolution by 1, 2, and 3 bits to obtain an effective ADC resolution of 11-
bit, 12-bit, or 13-bit respectively without CPU intervention.
Input Voltage
V_REF x 1023/1024
V_REF x 512/1024
V_REF x 511/1024
0
Repeat Count = 4
Shift Right = 1
11-Bit Result
0x07F7
0x0400
0x03FE
0x0000
Repeat Count = 16
Shift Right = 2
12-Bit Result
0x0FFC
0x0800
0x04FC
0x0000
Repeat Count = 64
Shift Right = 3
13-Bit Result
0x1FF8
0x1000
0x0FF8
0x0000
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