C8051F970-A-GM Datasheet, PDF (203/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
The module provides the following capabilities:
Single cycle operation
Multiply-accumulate or multiply only
Support for integer or fractional operations
Support for signed or unsigned operations
Rounding with saturation
Auto-increment or constant A and/or B registers
Logical 1-bit or multiple bit shift of accumulator left or right
Negation of accumulator, A, and/or B registers
DMA support for repetitive operations on large arrays of data.
Signed and unsigned alignment (right shift in bytes) of accumulator result
22.1. Special Function Registers
There are fifteen special function register (SFR) locations associated with MAC0. Six of these registers are related
to configuration and operation, while the other nine are used to store multi-byte input and output data for MAC0.
The configuration registers MAC0CF0, MAC0CF1, MAC0CF2 are used to configure and control MAC0. The status
register MAC0STA contains flags to indicate overflow and interrupt conditions, MAC operation completion, as well
as zero result. The 16-bit MAC0A (MAC0AH:MAC0AL) and MAC0B (MAC0BH:MAC0BL) registers are used as
inputs to the multiplier. Figure 22.1 shows a 41-bit accumulator—but only 40 bits can be read by the MCU or DMA
via the MAC0 Accumulator. The MAC0 Accumulator consists of five SFRs: MAC0OVF, MAC0ACC3, MAC0ACC2,
MAC0ACC1, and MAC0ACC0. The primary result of a MAC0 operation is available from the Accumulator registers
after the appropriate rounding, saturation or byte-realignment has been performed.
22.2. Integer and Fractional Math
MAC0 can perform math operations in unsigned or signed mode—this is controlled by the SIGNEDEN signed
mode selection bit. MAC0 is capable of interpreting the 16-bit inputs stored in MAC0A and MAC0B as integers or
as fractional numbers. When the FRACMD bit (MAC0CF0.4) is cleared to 0, the inputs are treated as 16-bit integer
values. After a MAC operation, the internal 41-bit accumulator will contain the integer result. Figure 22.2 shows
how integers are stored in the SFRs.
MAC0A and
HighByte
LowByte
s*2^15 2^14 2¹³ 2¹² 2¹¹ 2¹⁰ 2⁹ 2⁸ 2⁷ 2⁶ 2⁵ 2⁴ 2³ 2² 2¹ 2⁰
If(MAC0SN==1),s=Ͳ1,otherwises=1
MAC0AccumulatorBitWeighting
MAC0OVR
s*2^39 2^38 

MAC0ACC3:MAC0ACC2:MAC0ACC1:MAC0ACC0
2³² 2³¹ 2³⁰ 2²⁹ 2²⁸ 

2⁴ 2³ 2² 2¹ 2⁰
s=signofresult(1orͲ1)
Figure 22.2. Integer Mode Data Representation
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