C8051F970-A-GM Datasheet, PDF (354/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Table 29.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0)
Values Read
Values to
Write
Current SMbus State
Typical Response Options
1110 0 0 X A master START was generated.
Load slave address + R/W into 0 0 X 1100
SMB0DAT.
0
0
0
A master data or address byte was
transmitted; NACK received.
Set STA to restart transfer.
Abort transfer.
1 0 X 1110
01X —
Load next data byte into SMB0- 0 0 X 1100
DAT.
1100
0
0
1
A master data or address byte was
transmitted; ACK received.
End transfer with STOP.
01X —
End transfer with STOP and start 1 1 X —
another transfer.
Send repeated START.
1 0 X 1110
Switch to Master Receiver Mode 0 0 X 1000
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
0 0 1 1000
Send NACK to indicate last byte, 0 1 0 —
and send STOP.
Send NACK to indicate last byte, 1 1 0 1110
and send STOP followed by
START.
1000
1
0
X
A master data byte was received; ACK
requested.
Send ACK followed by repeated
START.
1
0
1
1110
Send NACK to indicate last byte, 1 0 0 1110
and send repeated START.
Send ACK and switch to Master 0 0 1 1100
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas- 0 0 0 1100
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
Rev 1.0
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