C8051F970-A-GM Datasheet, PDF (192/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 21.3. DMA0MINT: DMA0 Mid-Point Interrupt Flags
Bit
7
6
5
4
Name Reserved CH6MI
CH5MI
CH4MI
Type
R
RW
RW
RW
Reset
0
0
0
0
SFR Page = 0xF; SFR Address: 0x88 (bit-addressable)
3
CH3MI
RW
0
2
CH2MI
RW
0
1
CH1MI
RW
0
0
CH0MI
RW
0
Bit
Name
Function
7
Reserved Must write reset value.
6
CH6MI Channel 6 Mid-Point Interrupt Flag.
0: No mid-point Interrupt generated.
1: Mid-point Interrupt generated in channel 6.
5
CH5MI Channel 5 Mid-Point Interrupt Flag.
0: No mid-point Interrupt generated.
1: Mid-point Interrupt generated in channel 5.
4
CH4MI Channel 4 Mid-Point Interrupt Flag.
0: No mid-point Interrupt generated.
1: Mid-point Interrupt generated in channel 4.
3
CH3MI Channel 3 Mid-Point Interrupt Flag.
0: No mid-point Interrupt generated.
1: Mid-point Interrupt generated in channel 3.
2
CH2MI Channel 2 Mid-Point Interrupt Flag.
0: No mid-point Interrupt generated.
1: Mid-point Interrupt generated in channel 2.
1
CH1MI Channel 1 Mid-Point Interrupt Flag.
0: No mid-point Interrupt generated.
1: Mid-point Interrupt generated in channel 1.
0
CH0MI Channel 0 Mid-Point Interrupt Flag.
0: No mid-point Interrupt generated.
1: Mid-point Interrupt generated in channel 0.
Note: Mid-point Interrupt flag is set when the offset address DMA0NAOH/L equals to half of data transfer size DMA0NSZH/L
if the transfer size is an even number or half of data transfer size DMA0NSZH/L plus one if the transfer size is an odd
number. Firmware must clear this flag. The mid-point interrupt is enabled by setting the MIEN bit in the DMA0NCF
register with DMA0SEL configured for the corresponding channel.
Rev 1.0
193