C8051F970-A-GM Datasheet, PDF(371/454 Page) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

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C8051F970-A-GM Datasheet, PDF (371/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

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C8051F97x

30.5.2. I2C Read Sequence (CPU mode)

Figure 30.6 shows the details of how the I2C0STAT status bits change during an I2C Read data transfer.

I2C0 module â CPU mode â clock stretch â Read

1

Sleep

Active

2

S SLA R A

3

DB0 A

DB1 A

4

DB2 N Sr SLA R A

xa

b

c

d

1 SLA+R wakes CPU from sleep. SLA is ACK if BUSY was 0.

xe

5

DB3 N P

fg

S = START

P = STOP

A = ACK

N = NACK

R = Read

W = Write

Sr = repeated START

Shaded blocks are generated by

Slave device

2 INT generated. CPU writes DB0 into I2C0DOUT. SCL is held until CPU clears I2C0INT. CPU clears I2C0INT, releasing SCL

3 SCL held low; NACK bit reads â0â; CPU writes DB1 into I2C0DOUT and clears I2C0INT

4

NACK switches I2C slave to IDLE state and generates INT. Any following DB are ignored. If RpStart follows after NACK, the

START sticky bit will be set, but no interrupt.

5 STOP generates interrupt. No Clock Stretch. CPU clears I2C0INT

No int x

I2C0 int a

I2C0 int b

I2C0 int c

I2C0 int d

I2C0 int e

I2C0 int f

I2C0 int g

I2C0STAT = x1001000 at 8th SCL rising edge

I2C0STAT = x1101001; CPU clears START. CPU writes DB0 into I2C0DOUT and clears I2C0INT

I2C0STAT = x1100001; CPU writes DB1 into I2C0DOUT and clears I2C0INT

I2C0STAT = x1100001; CPU writes DB2 into I2C0DOUT and clears I2C0INT

I2C0STAT = x0110001; CPU prepares for STOP or RpStart and clears I2C0INT and clears NACK

I2C0STAT = x1101001; CPU clears START. CPU writes DB3 into I2C0DOUT and clears I2C0INT

I2C0STAT = x0110001; CPU prepares for STOP or RpStart and clears I2C0INT and clears NACK

I2C0STAT = x0100100; CPU clears STOP and clears I2C0INT

* At a, b, c, d, e, f : Bits are set/cleared at 9th SCL falling edge. CPU clears I2C0INT to release SCL

Figure 30.6. Typical I2C Read Sequence in CPU Mode

Note that the I2C Master MUST always generate a NACK before it can generate a repeated START bit or a STOP

bit. This is because the NACK will cause the I2C Slave to release the SDA line for the I2C Master to generate the

START or STOP bit.

30.5.3. I2C Write Sequence (DMA mode)

Figure 30.7 shows the details of how the I2C0STAT status bits change during an I2C Write data transfer.

372

Rev 1.0

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