C8051F970-A-GM Datasheet, PDF (174/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
While in the SPI0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt,
while the SPI0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector to the high priority
PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to access the PCA’s special
function registers into the SFRPAGE register, SFR page 0x00. The value that was in the SFRPAGE register before
the PCA interrupt (SFR page 0x00 for SPI0) is pushed down the stack into SFRNEXT. Likewise, the value that was
in the SFRNEXT register before the PCA interrupt (in this case SFR page 0x0F for I2C0STAT) is pushed down to
the SFRLAST register, the bottom of the stack. Note that a value stored in SFRLAST (via a previous software write
to the SFRLAST register) will be overwritten. See Figure 20.5.
SFRPAGE
pushed to
SFRNEXT
SFRNEXT
pushed to
SFRLAST
SFR Page 0x00
Automatically
pushed on stack
in SFRPAGE on
PCA interrupt
0x00
(PCA0)
0x00
(SPI0)
0x0F
(I2C0STAT)
SFR Page
Stack SFRs
SFRPAGE
SFRNEXT
SFRLAST
Figure 20.5. SFR Page Stack Upon PCA Interrupt Occurring During a SPI0 ISR
Rev 1.0
175