C8051F970-A-GM Datasheet, PDF (114/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
17.9. ADC Control Registers
Register 17.1. ADC0CN: ADC0 Control
Bit
7
6
5
4
3
2
1
0
Name ADEN ADBMEN ADINT ADBUSY ADWINT
ADCM
Type
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xE8 (bit-addressable)
Table 17.2. ADC0CN Register Bit Descriptions
Bit
Name
Function
7
ADEN ADC Enable.
0: Disable ADC0 (low-power shutdown).
1: Enable ADC0 (active and ready for data conversions).
6
ADBMEN Burst Mode Enable.
Important Note: Burst Mode must be disabled if CS0 is active. This is true regardless of
the ADC0MX configuration.
0: ADC0 Burst Mode Disabled.
1: ADC0 Burst Mode Enabled.
5
ADINT Conversion Complete Interrupt Flag.
Set by hardware upon completion of a data conversion (ADBMEN=0), or a burst of con-
versions (ADBMEN=1). Can trigger an interrupt. Must be cleared by firmware.
4
ADBUSY ADC Busy.
Writing 1 to this bit initiates an ADC conversion when ADCM = 000. This bit should not
be polled to indicate when a conversion is complete. Instead, the ADINT bit should be
used when polling for conversion completion.
3
ADWINT Window Compare Interrupt Flag.
Set by hardware when the contents of ADC0H:ADC0L fall within the window specified by
ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL. Can trigger an interrupt. Must be
cleared by firmware.
2:0
ADCM Start of Conversion Mode Select.
Specifies the ADC0 start of conversion source. All remaining bit combinations are
reserved.
000: ADC0 conversion initiated on write of 1 to ADBUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 3.
100: ADC0 conversion initiated on rising edge of CNVSTR.
101-111: Reserved.
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