C8051F970-A-GM Datasheet, PDF (435/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 33.3. PCA0PWM: PCA PWM Configuration
Bit
7
6
5
4
3
2
1
0
Name ARSEL
ECOV
COVF
Reserved
CLSEL
Type
RW
RW
RW
R
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xDF
Table 33.6. PCA0PWM Register Bit Descriptions
Bit
Name
Function
7
ARSEL Auto-Reload Register Select.
This bit selects whether to read and write the normal PCA capture/compare registers
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function is
used to define the reload value for 9 to 11-bit PWM modes. In all other modes, the Auto-
Reload registers have no function.
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6
ECOV Cycle Overflow Interrupt Enable.
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA interrupts.
1: A PCA interrupt will be generated when COVF is set.
5
COVF Cycle Overflow Flag.
This bit indicates an overflow of the 8th to 11th bit of the main PCA counter (PCA0). The
specific bit used for this flag depends on the setting of the Cycle Length Select bits. The
bit can be set by hardware or firmware, but must be cleared by firmware.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
4:2
Reserved Must write reset value.
1:0
CLSEL Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM cycle.
This affects all channels configured for PWM which are not using 16-bit PWM mode.
These bits are ignored for individual channels configured to 16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
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Rev 1.0