C8051F970-A-GM Datasheet, PDF (98/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
RAM and SFR register contents are preserved in sleep mode as long as the voltage on V_DD does not fall below
VPOR. The PC counter and all other volatile state information is preserved allowing the device to resume code
execution upon waking up from sleep mode. The following wake-up sources can be configured to wake the device
from sleep mode:
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
I2C0 Address Match
The V_DD supply monitor can be disabled to save power by writing 1 to the MONDIS (PMU0MD.5) bit. When the
V_DD supply monitor is disabled, all reset sources will trigger a full POR and will re-enable the V_DD supply monitor.
In addition, any falling edge on RST (due to a pin reset or a noise glitch) will cause the device to exit sleep mode.
In order for the MCU to respond to the pin reset event, software must not place the device back into sleep mode for
a period of 15 µs. The PMU0CF register may be checked to determine if the wake-up was due to a falling edge on
the RST pin. If the wake-up source is not due to a falling edge on RST, there is no time restriction on how soon
software may place the device back into sleep mode. A 4.7 k pullup resistor to V_DD is recommend for RST to
prevent noise glitches from waking the device.
16.6. Low Power Active Mode
Running in normal active mode can waste a significant amount of amount of power by clocking unused peripherals.
Low power active mode in C8051F97x devices allows control of clocking activity in the clock tree, which enables
firmware to shut off clocking to unused peripherals and save power.
Setting bit 1 and 2 of CLKMODE register causes the CIP-51 to enter low power active mode as soon as the
instruction that sets the bits completes execution. CPU, all the analog and digital peripherals remain active except
those whose clocks are turned off by user. The CPU will not be able to access SFR of peripherals on inactive
branches of the clock tree. Refer to Figure 16.1 for more information on how modules receive or request for
clocks in low power modes. It is important that firmware configures bit 4 to 7 of PCLKEN register on
page 249 to ensure desired clock gating of peripherals during low power active mode. For example, if UART
is supposed to be active during low power active mode, according to the PCLKEN register description bit 4 should
be set. However, that is not sufficient in this case because Timer 1 is needed for UART Baud rate generation. As a
consequence, bit 7 should be set as well for proper UART operation.
Low power active mode is terminated when the CLKMODE register is programmed to 0x00 or a reset occurs.
Systems that use all the peripherals and always stay in the active mode may not find improvement in power
consumption in the low power active mode due overhead logic required for this implementation.
16.7. Low Power Idle Mode
In this mode of operation, the CPU is halted and clocks supplied to unused peripherals can be shut down to save
power. Clocks of these peripherals can be enabled or disabled by programming bits 0 to 3 of PCLKEN register
accordingly on page 249. The device should be put to low power mode by setting bits 1 and 2 of CLKMODE
register. The last step necessary to put device in low power idle mode is to set the Idle Mode Select bit (PCON.0)
to 1. The CPU will be halted and the device will enter low-power idle mode as soon as the instruction that sets the
Idle Mode Select bit completes execution. As a result, configuration of peripherals clock gating through PCLKEN
register and CLKMODE register should be properly prepared before the Idle Mode Select bit in PCON is set. All
internal registers and memory maintain their original data. All the analog and digital peripherals remain active
except those whose clocks are turned off by user. Modules that are capable of requesting for clocks can do so at
any time. Refer to Figure 16.1 for more information on how modules receive or request for clocks in low power
modes.
Note: To ensure the MCU enters a low power state upon entry into Low Power Idle mode, the one-shot circuit should be
enabled by clearing the BYPASS bit (FLSCL.6).
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Rev 1.0