C8051F970-A-GM Datasheet, PDF (365/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
30.1. Supporting Documents
It is assumed that the reader is familiar or has access to the following supporting documents:
The I²C-bus specification and the user manual Rev. 0.3.
30.2. The I²C Configuration
Figure 30.2 shows a typical I²C configuration. The I²C specification allows any recessive voltage between 3.0 and
5.0 V; different devices on the bus may operate at different voltage levels.
Note: The port pins on the C8051F97x devices are not 5 V tolerant, therefore, the device may only be used in I²C networks
where the supply voltage does not exceed V_DD.
The bidirectional SCL and SDA lines must be connected to a positive power supply voltage through a pull-up
resistor or similar circuit. Every device connected to the bus must have an open-drain or open-collector output for
both the SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum
number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed
the specifications defined in the I²C standard.
VDD = 3 V
VDD = 3 V
VDD = 3 V
VDD = 3 V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Figure 30.2. Typical I²C Configuration
30.3. I2CSLAVE0 Operation
The I2CSLAVE0 peripheral supports two types of data transfers: I²C Read data transfers where data is transferred
from the C8051F97x’s I²C slave peripheral to an I²C master, and I²C Write data transfers where data is transferred
from an I²C master to the C8051F97x’s I²C slave peripheral. The I²C master initiates both types of data transfers
and provides the serial clock pulses that the I²C slave peripheral detects on the SCL pin.
A typical I²C transaction consists of a START condition followed by an address byte (Bits7-1: 7-bit slave address;
Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are received are
acknowledged (ACK) with a low SDA during a high SCL (refer to Figure 30.3).
SCL
SDA
SLA6
SLA5-0
R/W
D7
D6-0
START
Slave Address + R/W
ACK
Data Byte
Figure 30.3. I²C Transaction
NACK
STOP
366
Rev 1.0