C8051F970-A-GM Datasheet, PDF (202/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
22. Multiply and Accumulate (MAC0)
The C8051F97x devices include a multiply and accumulate engine which can be used to speed up many
mathematical operations. MAC0 contains a 16-by-16 bit multiplier and a 40-bit adder, which can perform integer or
fractional multiply-accumulate and multiply operations in a single SYSCLK cycle. Figure 22.1 shows a block
diagram of the MAC0 subsystem and its associated SFRs.
APOSTINC
MAC0 A Register
MAC0AH
MAC0AL
MAC0 B Register
MAC0BH
MAC0BL
BPOSTINC
SIGNEDEN
MBSHIFT
SHIFTDIR
1 bit shift
Flags Logic
16 x 16 Multiply
Adder
BUSY
ACCMD
ADMASRC
BDMASRC
1
0
0
MAC0 Data
Transfer Logic
Data Bus
0 1 ACCNEGATE
41-bit Accumulator
Negate
SATURATE Rounding Alignment
SIGNEDEN
ACCALIGN
DMA control
signals
SIGNEDEN
10
ROUND
DMA control
signals
MAC0 Accumulator
MAC0OVR MAC0ACC3 MAC0ACC2 MAC0ACC1 MAC0ACC0
Figure 22.1. MAC0 Block Diagram
Rev 1.0
203