C8051F970-A-GM Datasheet, PDF (394/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
32.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate
in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit in TMR2CN defines the Timer 2 oper-
ation mode. Timer 2 can also be used in Capture Mode to measure the SmaRTClock or the Comparator 0 period
with respect to another oscillator. The ability to measure the Comparator 0 period with respect to the system clock
makes using Touch Sense switches very easy.
Timer 2 may be clocked by the system clock, the system clock divided by 12, SmaRTClock divided by 8, or
Comparator 0 output. Note that the SmaRTClock divided by 8 and Comparator 0 output is synchronized with the
system clock.
32.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT in the TMR2CN register is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can
be clocked by SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8, or Comparator 0 output. As the 16-bit
timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2 reload registers
(TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 32.4, and the Timer 2 High Byte
Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is set), an interrupt will be generated on
each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled and the TF2LINT bit is set, an interrupt will be
generated each time the lower 8 bits (TMR2L) overflow from 0xFF to 0x00.
T2XCLK[1:0]
SYSCLK / 12
00
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 1 0
SmaRTClock / 8
01
0
TR2
1
SYSCLK
TL2
Overflow
To SMBus
TCLK
TMR2L TMR2H
TMR2RLL TMR2RLH
Reload
To ADC,
SMBus
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK
Figure 32.4. Timer 2 16-Bit Mode Block Diagram
Interrupt
Rev 1.0
395