C8051F970-A-GM Datasheet, PDF (247/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
24.5. Clock Selection Control Registers
Register 24.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
1
0
Name CLKRDY
CLKDIV
Reserved
CLKSL
Type
R
RW
R
RW
Reset
0
0
1
1
0
1
0
0
SFR Page = 0x0; SFR Address: 0xA9
Bit
Name
Function
7
CLKRDY System Clock Divider Clock Ready Flag.
0: The selected clock divide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
6:4
CLKDIV Clock Source Divider.
This field controls the divider applied to the clock source selected by CLKSL. The output
of this divider is the system clock (SYSCLK).
000: SYSCLK is equal to selected clock source divided by 1.
001: SYSCLK is equal to selected clock source divided by 2.
010: SYSCLK is equal to selected clock source divided by 4.
011: SYSCLK is equal to selected clock source divided by 8.
100: SYSCLK is equal to selected clock source divided by 16.
101: SYSCLK is equal to selected clock source divided by 32.
110: SYSCLK is equal to selected clock source divided by 64.
111: SYSCLK is equal to selected clock source divided by 128.
3
Reserved Must write reset value.
2:0
CLKSL Clock Source Select.
Selects the oscillator to be used as the undivided system clock source.
000: Clock derived from the internal precision High-Frequency Oscillator.
001: Clock derived from the External Oscillator circuit.
010: Clock derived from the Internal Low Power Oscillator divided by 8.
011: Clock derived from the RTC.
100: Clock derived from the Internal Low Power Oscillator.
101-111: Reserved.
248
Rev 1.0