C8051F970-A-GM Datasheet, PDF (408/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

32.6. Timer 2 Registers
C8051F97x
Register 32.8. TMR2CN: Timer 2 Control
Bit
7
6
5
4
3
2
1
0
Name TF2H
TF2L
TF2LEN TF2CEN T2SPLIT
TR2
T2XCLK
Type
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = ALL; SFR Address: 0xC8 (bit-addressable)
Table 32.10. TMR2CN Register Bit Descriptions
Bit
Name
Function
7
TF2H Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16-bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2
interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt ser-
vice routine. This bit must be cleared by firmware.
6
TF2L Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will be
set when the low byte overflows regardless of the Timer 2 mode. This bit must be cleared
by firmware.
5
TF2LEN Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are also
enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
4
TF2CEN Timer 2 Capture Enable.
When set to 1, this bit enables Timer 2 Capture Mode. If TF2CEN is set and Timer 2
interrupts are enabled, an interrupt will be generated based on the selected input capture
source, and the current 16-bit timer value in TMR2H:TMR2L will be copied to
TMR2RLH:TMR2RLL.
3
T2SPLIT Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
2
TR2
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables TMR2H
only; TMR2L is always enabled in split mode.
Rev 1.0
409