C8051F970-A-GM Datasheet, PDF (80/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Table 13.1. Interrupt Summary
Interrupt Source Interrupt Priority
Vector Order
Pending Flag
Enable Flag
Priority
Control
Reset
0x0000
External Interrupt 0
(/INT0)
Timer 0 Overflow
External Interrupt 1
(/INT1)
Timer 1 Overflow
UART0
0x0003
0x000B
0x0013
0x001B
0x0023
Timer 2 Overflow 0x002B
SPI0
0x0033
SMB0
0x003B
SmaRTClock Alarm 0x0043
ADC0 Window
Comparator
0x004B
ADC0 End of
Conversion
0x0053
Programmable
Counter Array
0x005B
DMA0 Midpoint
0x0063
Operation Complete
DMA0 Endpoint
0x006B
Operation Complete
Timer 3 Overflow
0x0073
Port Match
0x0083
Top
None
N/A N/A Always Always High-
Enabled
est
0
IE0 (TCON.1)
Y
Y EX0 (IE.0) PX0 (IP.0)
1
TF0 (TCON.5)
Y
Y ET0 (IE.1) PT0 (IP.1)
2
IE1 (TCON.3)
Y
Y EX1 (IE.2) PX1 (IP.2)
3
TF1 (TCON.7)
Y
4
RI0 (SCON0.0)
Y
TI0 (SCON0.1)
5
TF2H (TMR2CN.7)
Y
TF2L (TMR2CN.6)
6
SPIF (SPI0CN.7)
Y
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
7
SI (SMB0CN.0)
Y
8
ALRM (RTC0CN.2)^*
N
9
AD0WINT
Y
(ADC0CN.3)
10 AD0INT (ADC0CN.5) Y
11
CF (PCA0CN.7)
Y
CCFn (PCA0CN.n)
12
CHn_MINT
Y
(DMA0MINT.n)
13 CHn_INT (DMA0INT.n) Y
14
TF3H (TMR3CN.7)
N
TF3L (TMR3CN.6)
16
None
Y ET1 (IE.3) PT1 (IP.3)
N ES0 (IE.4) PS0 (IP.4)
N ET2 (IE.5) PT2 (IP.5)
N ESPI0 (IE.6) PSPI0 (IP.6)
N
ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
N
ERTC0
(EIE1.1)
PRTC0
(EIP1.1)
N EWADC0 PWADC0
(EIE1.2)
(EIP1.2)
N
EADC0
(EIE1.3)
PADC0
(EIP1.3)
N
EPCA0
(EIE1.4)
PPCA0
(EIE1.4)
N EDMA0M PDMA0M
(EIE1.5)
(EIP1.5)
N
EDMA0
(EIE1.6)
PDMA0
(EIP1.6)
N ET3 (EIE1.7) PT3 (EIP1.7)
EMAT
(EIE2.1)
PMAT
(EIP2.1)
80
Rev 1.0