C8051F970-A-GM Datasheet, PDF (381/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Baud Rate Generator
(In Timer 1)
TL1
2
TX Clock
START
Detection
TH1
RX Timer
2
RX Clock
Figure 31.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload. The Timer 1 reload value should be set so that
overflows will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one
of six sources: SYSCLK, SYSCLK/4, SYSCLK/12, SYSCLK/48, the external oscillator clock/8, or an external input
T1. For any given Timer 1 overflow rate, the UART0 baud rate is determined by Equation 31.1.
UartBaudRate = ^1--  T1_Overflow_Rate
2
Equation 31.1. UART0 Baud Rate
Timer 1 overflow rate is selected as described in the Timer section. A quick reference for typical baud rates and
system clock frequencies is given in Table 31.1.
382
Rev 1.0