C8051F970-A-GM Datasheet, PDF (115/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 17.2. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
Name
ADSC
AD8BE
ADTM
ADGN
Type
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0x97
Table 17.3. ADC0CF Register Bit Descriptions
Bit
Name
Function
7:3
ADSC SAR Clock Divider.
This field sets the ADC clock divider value. It should be configured to be as close to the
maximum SAR clock speed as the datasheet will allow. The SAR clock frequency is
given by the following equation:
F_CLKSAR
=
--F---^A----^D---^C---^C---^L---^K---
ADSC + 1
F_ADCCLK is equal to the selected SYSCLK when ADBMEN is 0 and the high-frequency
oscillator when ADBMEN is 1.
2
AD8BE 8-Bit Mode Enable.
0: ADC0 operates in 10-bit mode (normal operation).
1: ADC0 operates in 8-bit mode.
1
ADTM Track Mode.
Selects between Normal or Delayed Tracking Modes.
0: Normal Track Mode. When ADC0 is enabled, conversion begins immediately following
the start-of-conversion signal.
1: Delayed Track Mode. When ADC0 is enabled, conversion begins 3 SAR clock cycles
following the start-of-conversion signal. The ADC is allowed to track during this time.
0
ADGN Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
Rev 1.0
115