C8051F970-A-GM Datasheet, PDF (171/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
SFRPGEN Bit
Interrupt
Logic
CIP-51
SFRPAGE
SFRLAST
SFRLAST
Figure 20.2. SFR Page Stack
Automatic hardware switching of the SFR page on interrupts may be enabled or disabled as desired using the SFR
Automatic Page Control Enable Bit located in the SFR page Control Register (SFRPGCN). This function defaults to
“enabled” upon reset. In this way, the auto-switching function will be enabled unless disabled in software.
A summary of the SFR locations (address and SFR page) are provided in Table 9.1 on page 57 and Table 9.2 on
page 58. Each memory location in the map has an SFR page row, denoting the page in which that SFR resides.
Certain SFRs are accessible from all SFR pages. For example, the Port I/O registers P0, P1, P2, and P3 are avail-
able on all pages regardless of the SFRPAGE register value.
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