C8051F970-A-GM Datasheet, PDF (326/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

27.10. Reset Sources Control Registers
C8051F97x
Register 27.1. RSTSRC: Reset Source
Bit
7
6
5
Name RTC0RE FERROR Reserved
Type
RW
RW
RW
Reset
X
X
X
SFR Page = 0x0; SFR Address: 0xEF
4
SWRSF
RW
X
3
WDTRSF
RW
X
2
MCDRSF
RW
X
1
PORSF
RW
X
0
PINRSF
RW
X
Table 27.1. RSTSRC Register Bit Descriptions
Bit
Name
Function
7
RTC0RE RTC Reset Enable and Flag.
Read: This bit reads 1 if a RTC alarm or oscillator fail caused the last reset.
Write: Writing a 1 to this bit enables the RTC as a reset source.
6
FERROR Flash Error Reset Flag.
This read-only bit is set to '1' if a flash read/write/erase error caused the last reset.
5
Reserved Must write reset value.
4
SWRSF Software Reset Force and Flag.
Read: This bit reads 1 if last reset was caused by a write to SWRSF.
Write: Writing a 1 to this bit forces a system reset.
3
WDTRSF Watchdog Timer Reset Flag.
This read-only bit is set to '1' if a watchdog timer overflow caused the last reset.
2
MCDRSF Missing Clock Detector Enable and Flag.
Read: This bit reads 1 if a missing clock detector timeout caused the last reset.
Write: Writing a 1 to this bit enables the missing clock detector. The MCD triggers a reset
if a missing clock condition is detected.
1
PORSF Power-On / Supply Monitor Reset Flag, and Supply Monitor Reset Enable.
Read: This bit reads 1 anytime a power-on or supply monitor reset has occurred.
Write: Writing a 1 to this bit enables the supply monitor as a reset source.
0
PINRSF HW Pin Reset Flag.
This read-only bit is set to '1' if the RST pin caused the last reset.
Notes:
1. Reads and writes of the RSTSRC register access different logic in the device. Reading the register always returns
status information to indicate the source of the most recent reset. Writing to the register activates certain options as
reset sources. It is recommended to not use any kind of read-modify-write operation on this register.
2. When the PORSF bit reads back '1' all other RSTSRC flags are indeterminate.
3. Writing '1' to the PORSF bit when the supply monitor is not enabled and stabilized may cause a system reset.
Rev 1.0
327