C8051F970-A-GM Datasheet, PDF (305/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 26.21. P2MDOUT: Port 2 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
B7
B6
B5
B4
B3
B2
B1
B0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0xDD
Table 26.24. P2MDOUT Register Bit Descriptions
Bit
Name
7
B7
Port 2 Bit 7 Output Mode.
0: P2.7 output is open-drain.
1: P2.7 output is push-pull.
6
B6
Port 2 Bit 6 Output Mode.
0: P2.6 output is open-drain.
1: P2.6 output is push-pull.
5
B5
Port 2 Bit 5 Output Mode.
0: P2.5 output is open-drain.
1: P2.5 output is push-pull.
4
B4
Port 2 Bit 4 Output Mode.
0: P2.4 output is open-drain.
1: P2.4 output is push-pull.
3
B3
Port 2 Bit 3 Output Mode.
0: P2.3 output is open-drain.
1: P2.3 output is push-pull.
2
B2
Port 2 Bit 2 Output Mode.
0: P2.2 output is open-drain.
1: P2.2 output is push-pull.
1
B1
Port 2 Bit 1 Output Mode.
0: P2.1 output is open-drain.
1: P2.1 output is push-pull.
0
B0
Port 2 Bit 0 Output Mode.
0: P2.0 output is open-drain.
1: P2.0 output is push-pull.
Function
306
Rev 1.0