C8051F970-A-GM Datasheet, PDF (254/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
25.1. SmaRTClock Interface
The SmaRTClock Interface consists of two registers: RTC0ADR and RTC0DAT. These interface registers are
located on the CIP-51’s SFR map and provide access to the SmaRTClock internal registers listed in Table 25.1.
The SmaRTClock internal registers can only be accessed indirectly through the SmaRTClock Interface.
Table 25.1. SmaRTClock Internal Registers
SmaRTClock
Address
0x00–0x03
0x04
0x05
0x06
0x08–0x0B
SmaRTClock
Register
Register Name
CAPTUREn SmaRTClock Capture
Registers
RTC0CN
SmaRTClock Control
Register
RTC0XCN SmaRTClock Oscillator
Control Register
RTC0XCF SmaRTClock Oscillator
Configuration Register
ALARMn
SmaRTClock Alarm
Registers
Description
Four Registers used for setting the 32-bit
SmaRTClock timer or reading its current value.
Controls the operation of the SmaRTClock State
Machine.
Controls the operation of the SmaRTClock
Oscillator.
Controls the value of the progammable oscillator
load capacitance and enables/disables AutoStep.
Four registers used for setting or reading the 32-bit
SmaRTClock alarm value.
25.1.1. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The RTC0ADR
register selects the SmaRTClock internal register that will be targeted by subsequent reads or writes.
Recommended instruction timing is provided in this section. If the recommended instruction timing is not followed,
then BUSY (RTC0ADR.7) should be checked prior to each read or write operation to make sure the SmaRTClock
Interface is not busy performing the previous read or write operation. A SmaRTClock Write operation is initiated by
writing to the RTC0DAT register. Below is an example of writing to a SmaRTClock internal register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0XCN register at SmaRTClock Address 0x05.
3. Write 0x00 to RTC0DAT. This operation writes 0x00 to the internal RTC0CN register.
A SmaRTClock Read operation is initiated by setting the SmaRTClock Interface Busy bit. This transfers the
contents of the internal register selected by RTC0ADR to RTC0DAT. The transferred data will remain in RTC0DAT
until the next read or write operation. Below is an example of reading a SmaRTClock internal register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0XCN register at SmaRTClock Address 0x05.
3. Write 1 to BUSY. This initiates the transfer of data from RTC0XCN to RTC0DAT.
4. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommend instruction timing.
5. Read data from RTC0DAT. This data is a copy of the RTC0XCN register.
Note: The RTC0ADR and RTC0DAT registers will retain their state upon a device reset.
25.1.2. RTC0ADR Short Strobe Feature
Reads and writes to indirect SmaRTClock registers normally take 7 system clock cycles. To minimize the indirect
register access time, the Short Strobe feature decreases the read and write access time to 6 system clocks. The
Short Strobe feature is automatically enabled on reset and can be manually enabled/disabled using the SHORT
(RTC0ADR.4) control bit.
Recommended Instruction Timing for a single register read with short strobe enabled:
mov RTC0ADR, #095h
nop
nop
Rev 1.0
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