C8051F970-A-GM Datasheet, PDF (137/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
18.13. Adjusting CS0 For Special Situations
There are several configuration options in the CS0 module designed to modify the operation of the circuit and
address special situations. In particular, any circuit with more than 500  of series impedance between the sensor
and the device pin may require the adjustments detailed in this section for optimal performance. Typical
applications which may require adjustments include the following:
Touch panel sensors fabricated using a resistive conductor such as indium-tin-oxide (ITO).
Circuits using a high-value series resistor to isolate the sensor element for high ESD protection.
Capacitive sensors created using PCB traces should generally require no fine tuning, and the default settings for
CS0DT, CS0DR, CS0IA, CS0RP and CS0LP should be used.
18.13.1. Adjusting the CS0 Reset Timing
The CS0 module determines capacitance by discharging an external capacitor and then measuring how quickly
that capacitor charges. In order to do this, the external capacitor must be fully discharged before every test. There
are two timers inside the CS0 module which determine the timing for the reset (discharge) operation.
CS0 performs a two-stage discharge (double reset) of the external capacitor at the start of every bit conversion to
improve performance in high-noise environments. In this method, most of the charge in the external capacitor is
removed in a first reset stage through a low-resistance switch to ground. A second reset is then performed using a
high-resistance switch to ground. This second reset removes any ambient noise energy that might have been
captured in the external capacitor at the end of the first reset stage.
The lengths of both reset periods are independently adjustable. Longer periods are used when the external
capacitor is separated from the CS0 module by a large resistor (more than 500 ) because that series resistor
would slow the rate of discharge.
Determining the appropriate settings for CS0DT (the primary reset) and CS0DR (the secondary reset) are two of a
series of related adjustments which must be made when using CS0 to measure capacitive loads in the presence of
high resistance.
18.13.2. Adjusting Primary Reset Timing: CS0DT
Primary reset timing adjustment is performed to provide peak sensitivity for highly-resistive loads and peak linearity
for capacitive loads linked thorough a distributed resistance (such as an ITO touch panel) while minimizing the
required conversion time.
The adjustment for CS0DT should be performed while CS0DR and CS0IA bits are set at their maximum values
(CS0DR = 11b, CS0IA = 001b).
1. Begin the adjustment with CS0DT set to maximum delay (CS0DT = 111b). Measure the untouched
average CS0 result for the channel under test.
Note: When calibrating CS0 for use with an ITO panel, consider the use of an artificial finger: a small (¼” O.D.) washer (#2
regular, #4 narrow) wired through a 1000 pF capacitor to ground. Select a touch point at the on the farthest end of the
longest row. Find the point where maximum response is returned from the CS0 conversion.
2. Record the average touched CS0 value with CS0DT = 111b. The touched value should be higher than the
untouched value. The magnitude of the difference between the touched and untouched average CS0
values is the figure of merit for touch sensitivity.
3. Decrease the primary reset time CS0DT by one and repeat the touched and untouched CS0
measurements. Repeat this step until values have been recorded for all eight CS0DT settings. As the
CS0DT setting decreases, the average sensitivity of the CS0 value may begin to decrease significantly.
4. CS0DT should be set high enough that there is not a significant decrease in sensitivity due to resistance.
Select the CS0DT setting that occurred prior to the observed drop in CS0 touch sensitivity.
Rev 1.0
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