C8051F970-A-GM Datasheet, PDF (56/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
8.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-
purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these
banks may be enabled at a time. Two bits in the program status word (PSW) register, RS0 and RS1, select the
active register bank. This allows fast context switching when entering subroutines and interrupt service routines.
Indirect addressing modes use registers R0 and R1 as index registers.
8.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through
0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of
the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F
has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source
or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the
byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
8.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using
the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed on the stack is
placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the
first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1.
Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not
being used for data storage. The stack depth can extend up to 256 bytes.
8.2.2. External RAM
C8051F97x devices have 4 kB or 8 kB of on-chip RAM mapped into the external data memory space. All of these
address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or
using MOVX indirect addressing mode. Note: the 16-bit MOVX instruction is also used for writes to the flash
memory. See Section “10. Flash Memory” on page 65 for details. The MOVX instruction accesses XRAM by
default.
For a 16-bit MOVX operation (@DPTR), the upper 8 bits of the 16-bit external data memory address word are
“don't cares”. As a result, addresses 0x0000 through 0x00FF are mapped modulo style over the entire 64 k
external data memory address range. For example, the XRAM byte at address 0x0000 is shadowed at addresses
0x0100, 0x0200, 0x0300, 0x0400, etc.
The C8051F97x devices implement the upper four bytes of external RAM as a 128-bit Unique Identifier. More
information can be found in “Device Identification and Unique Identifier” on page 76.
8.2.3. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The
SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the
SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and
access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining
compatibility with the MCS-51™ instruction set.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from
0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-addressable as
well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are
reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided.
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