C8051F970-A-GM Datasheet, PDF (195/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 21.6. DMA0NCF: DMA0 Channel Configuration
Bit
7
6
5
4
3
2
1
0
Name
IEN
MIEN
STALL ENDIAN Reserved
PERIPH
Type
RW
RW
RW
RW
R
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0xD8 (bit-addressable)
Bit
Name
Function
7
IEN
Full-Length Interrupt Enable.
This bit enables DMA0 full-length interrupt requests for the selected channel.
0: Disable the DMA0 full-length interrupt request of the selected channel.
1: Enable the DMA0 full-length interrupt request of the selected channel.
6
MIEN Mid-Point Interrupt Enable.
This bit enables DMA0 mid-point interrupt requests for the selected channel.
0: Disable the DMA0 mid-point interrupt request of the selected channel.
1: Enable the DMA0 mid-point interrupt request of the selected channel.
5
STALL Channel Stall.
Setting this bit stalls the DMA transfer on the selected channel. A stalled channel cannot
initiate new DMA transfers. The DMA0 transfer of the stalled channel resumes where it
was only when this bit is cleared by firmware.
0: The DMA transfer of the selected channel is not stalled.
1: The DMA transfer of the selected channel is stalled.
4
ENDIAN Data Transfer Endianness.
This bit sets the byte order of the XRAM data.
0: Data is written to and read from XRAM in little endian order.
1: Data is written to and read from XRAM in big endian order.
3
Reserved Must write reset value.
2:0
PERIPH Peripheral Transfer Select.
This field selects the DMA0 transfer function for the selected channel.
000-001: Reserved.
010: The DMA channel transfers from XRAM to the MAC A register.
011: The DMA channel transfers from XRAM to the MAC B register.
100: The DMA channel transfers from XRAM to the MAC accumulator registers.
101: The DMA channel transfers from the MAC accumulator registers to XRAM.
110: The DMA channel transfers from the I2C Slave data register to XRAM.
111: The DMA channel transfers from XRAM to the I2C Slave data register.
Note: This register is a DMA channel indirect register. Select the desired channel first using the DMA0SEL register.
196
Rev 1.0