C8051F970-A-GM Datasheet, PDF (248/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 24.2. PCLKEN: Low Power Peripheral Clock Enable
Bit
7
6
5
4
3
2
1
0
Name PCLKEN7 PCLKEN6 PCLKEN5 PCLKEN4 PCLKEN3 PCLKEN2 PCLKEN1 PCLKEN0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xF6
Bit
Name
Function
7
PCLKEN7 Low Power Active Mode Peripheral Set 3 Enable.
0: Disable clocks of Timer 0, 1, 2, CRC0, C2, RTC0, and Port Match in low power active
mode.
1: Enable clocks of Timer 0, 1, 2, CRC0, C2, RTC0, and Port Match in low power active
mode.
6
PCLKEN6 Low Power Active Mode Peripheral Set 2 Enable.
0: Disable clocks of PCA0, CS0, and ADC0 in low power active mode.
1: Enable clocks of PCA0, CS0, and ADC0 in low power active mode.
5
PCLKEN5 Low Power Active Mode Peripheral Set 1 Enable.
0: Disable clocks of MAC0 in low power active mode.
1: Enable clocks of MAC0 in low power active mode.
4
PCLKEN4 Low Power Active Mode Peripheral Set 0 Enable.
0: Disable clocks of UART0, Timer 3, SPI0, and I2C0 in low power active mode.
1: Enable clocks of UART0, Timer 3, SPI0, and I2C0 in low power active mode.
3
PCLKEN3 Low Power Idle Mode Peripheral Set 3 Enable.
0: Disable clocks of Timer 0, 1, 2, CRC0, C2, RTC0, and Port Match in low power idle
mode.
1: Enable clocks of Timer 0, 1, 2, CRC0, C2, RTC0, and Port Match in low power idle
mode.
2
PCLKEN2 Low Power Idle Mode Peripheral Set 2 Enable.
0: Disable clocks of PCA0, CS0, and ADC0 in low power idle mode.
1: Enable clocks of PCA0, CS0, and ADC0 in low power idle mode.
1
PCLKEN1 Low Power Idle Mode Peripheral Set 1 Enable.
0: Disable clocks of MAC0 in low power idle mode.
1: Enable clocks of MAC0 in low power idle mode.
0
PCLKEN0 Low Power Idle Mode Peripheral Set 0 Enable.
0: Disable clocks of UART0, Timer 3, SPI0, and I2C0 in low power idle mode.
1: Enable clocks of UART0, Timer 3, SPI0, and I2C0 in low power idle mode.
Rev 1.0
249