C8051F970-A-GM Datasheet, PDF (351/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
29.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a
transmitter during the address byte, and a receiver during all data bytes. The SMBus interface generates the
START condition and transmits the first byte containing the address of the target slave and the data direction bit. In
this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA
while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each received
byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK, and
then post the interrupt. It is important to note that the appropriate ACK or NACK value should be set up by
the software prior to receiving the byte when hardware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to the ACK
bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set
and a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0DAT is written while an
active Master Receiver. Figure 29.6 shows a typical master read sequence. Two received data bytes are shown,
though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur at different
places in the sequence, depending on whether hardware ACK generation is enabled. The interrupt occurs before
the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
RA
Data Byte
A
Data Byte
NP
Interrupts with Hardware ACK Disabled (EHACK = 0)
Received by SMBus
Interface
Transmitted by
SMBus Interface
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Figure 29.6. Typical Master Read Sequence
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