C8051F970-A-GM Datasheet, PDF (395/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
32.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-
reload mode as shown in Figure 32.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload
value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is always running when
configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or
Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or the
clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
T2MH
0
0
0
0
1
T2XCLK[1:0] TMR2H Clock
Source
00
SYSCLK / 12
01
SmaRTClock / 8
10
Reserved
11
Comparator 0
X
SYSCLK
T2ML
0
0
0
0
1
T2XCLK[1:0] TMR2L Clock
Source
00
SYSCLK / 12
01
SmaRTClock / 8
10
Reserved
11
Comparator 0
X
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows from
0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time TMR2H overflows. If
Timer 2 interrupts are enabled and TF2LINT (TMR2CN.5) is set, an interrupt is generated each time either TMR2L
or TMR2H overflows. When TF2LINT is enabled, software must check the TF2H and TF2L flags to determine the
source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags are not cleared by hardware and must be man-
ually cleared by software.
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
TMOD
GCT TGCT T
A / 11A / 00
T T MM T T MM
E110E010
1
0
IT01CF
IIIIIIII
NNNNNNNN
11110000
PSSSPSSS
LLLLLLLL
210 210
Pre-scaled Clock
0
0
SYSCLK
1
1
T0
Crossbar
TR0
GATE0
TCLK
TL0
(8 bits)
/INT0
IN0PL _XOR
TH0
(8 bits)
Reload
Figure 32.5. Timer 2 8-Bit Mode Block Diagram
TF1
TR1
TF0
Interrupt
TR0
IE1
IT1
IE0
IT0
396
Rev 1.0