C8051F970-A-GM Datasheet, PDF (433/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
33.5. PCA0 Control Registers
Register 33.1. PCA0CN: PCA Control
Bit
7
6
5
4
3
2
1
0
Name
CF
CR
Reserved
CCF2
CCF1
CCF0
Type
RW
RW
R
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xD8 (bit-addressable)
Table 33.4. PCA0CN Register Bit Descriptions
Bit
Name
Function
7
CF
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When
the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to
vector to the PCA interrupt service routine. This bit is not automatically cleared by hard-
ware and must be cleared by firmware.
6
CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: Stop the PCA Counter/Timer.
1: Start the PCA Counter/Timer running.
5:3
Reserved Must write reset value.
2
CCF2 PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine.
This bit is not automatically cleared by hardware and must be cleared by firmware.
1
CCF1 PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine.
This bit is not automatically cleared by hardware and must be cleared by firmware.
0
CCF0 PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine.
This bit is not automatically cleared by hardware and must be cleared by firmware.
434
Rev 1.0