C8051F970-A-GM Datasheet, PDF (285/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
26.7. Port Configuration Registers
Register 26.1. XBR0: Port I/O Crossbar 0
Bit
7
6
5
4
3
2
1
0
Name ECIE
PCA0ME
SYSCKE SMB0E
SPI0E
URT0E
Type
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0x95
Table 26.4. XBR0 Register Bit Descriptions
Bit
Name
Function
7
ECIE PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
6:4
PCA0ME PCA Module I/O Enable.
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100-111: Reserved.
3
SYSCKE SYSCLK Output Enable.
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port pin.
2
SMB0E SMBus0 I/O Enable.
0: SMBus0 I/O unavailable at Port pins.
1: SMBus0 I/O routed to Port pins.
1
SPI0E SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. The SPI can be assigned either 3 or 4 GPIO pins.
0
URT0E UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX, RX routed to Port pins P0.4 and P0.5.
286
Rev 1.0