C8051F970-A-GM Datasheet, PDF (88/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Table 13.5. EIP1 Register Bit Descriptions
Bit
Name
Function
0
PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
88
Rev 1.0