C8051F970-A-GM Datasheet, PDF (208/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Original41Ͳbitaccumulatordata(beforeshifting)
Bitposition: 40 39^ 38^ 37 7 6 5 4 3 2 1 0

d40 d39 d38 d37 d7 d6 d5 d4 d3 d2 d1 d0

Signedmode1Ͳbitshiftleftresult
Bitposition 40 39^ 38^ 37 7 6 5 4 3 2 1 0

d40 d38 d37 d36 d6 d5 d4 d3 d2 d1 d0 0

Signedmode1Ͳbitshiftrightresult
Bitposition 40 39^ 38^ 37 7 6 5 4 3 2 1 0

d40 d40 d39 d38 d8 d7 d6 d5 d4 d3 d2 d1

Unsignedmode1Ͳbitshiftleftresult
Bitposition 40 39^ 38^ 37 7 6 5 4 3 2 1 0

d39 d38 d37 d36 d6 d5 d4 d3 d2 d1 d0 0

Unsignedmode1Ͳbitshiftrightresult
Bitposition 40 39^ 38^ 37 7 6 5 4 3 2 1 0

0 d40 d39 d38 d8 d7 d6 d5 d4 d3 d2 d1

Figure 22.6. 1-Bit Shift of 41-Bit Accumulator in Signed and Unsigned Modes
22.8. Multi-Bit Shift Accumulator Operation
The MAC0 also includes a multi-bit arithmetic shift (up to 4 bits) function that can operate in DMA mode only. The
shift operation is only performed at the end of a MAC operation. The SHIFTDIR bit controls the direction of shift. To
enable multi-bit shifting on the Accumulator, the SHIFTEN bit must be set.
MBSHIFT = 0x00 : 1-bit shift
MBSHIFT = 0x01 : 2-bit shift
MBSHIFT = 0x02 : 3-bit shift
MBSHIFT = 0x03 : 4-bit shift
Rev 1.0
209