C8051F970-A-GM Datasheet, PDF (369/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
30.4.3. I2C0SLAD Slave Address Register
The I2CSLAVE0 peripheral can be configured to recognize a specific slave address and respond with an ACK
without any software intervention. This feature is enabled by software in the following sequence writes to the
I2CSLAVE0 registers;
1. Clearing BUSY bit in I2C0CNTL to enable automatic ACK response.
2. Writing the slave address to I2C0SLAD.
3. Setting I2C0SEL bit in I2C0CNTL to enable the SCL and SDA pads.
4. Setting I2C0EN bit in I2C0CNTL to enable the I2CSLAVE0 peripheral.
30.4.4. I2C0DIN Received Data Register
The I2C0DIN register holds the serial data that has just been received on the I²C bus and addressed to the local
device. When the I2CSLAVE0 is operating in CPU mode for I²C Write operations, software may safely read from
this register when the I2C0INT flag is set. It is not safe to read from this register in any one of the following
conditions:
The I2C0INT flag is cleared to logic 0.
The I2CSLAVE0 is operating in DMA mode for I²C Write operations.
When the I2CSLAVE0 is operating in DMA mode for I²C Write operations, software should access the received
data from the XRAM where the DMA has transferred the received data.
30.4.5. I2C0DOUT Transmit Data Register
The I2C0DOUT register holds the serial data that is to be transmitted on the I²C bus. When the I2CSLAVE0 is
operating in CPU mode for I²C Read operations, software may safely write to this register when the I2C0INT flag is
set. It is not safe to write to this register in any one of the following conditions:
The I2C0INT flag is cleared to logic 0
The I2CSLAVE0 is operating in DMA mode for I²C Read operations
When the I2CSLAVE0 is operating in DMA mode for I²C Read operations, software should setup the data to be
transmitted in XRAM and configure the DMA to transfer the data from XRAM to the I2C0DOUT register.
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