C8051F970-A-GM Datasheet, PDF (217/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 22.3. MAC0CF1: MAC0 Configuration 1
Bit
7
6
5
4
3
2
1
0
Name
MBSHIFT
SIGNEXP
SIGNEDE
N
MAC0BC BPOSTINC ADMASRC APOSTINC
Type
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0xC4
Bit
Name
Function
7:6 MBSHIFT Multi-Bit Accumulator Shift.
This field sets the number of bits hardware shifts the accumulator at the end of a MAC
operation in DMA mode if SHIFTEN is set to 1. The direction of the shift is determined by
the SHIFTDIR bit.
00: Shift the accumulator 1 bit.
01: Shift the accumulator by 2 bits.
10: Shift the accumulator by 3 bits.
11: Shift the accumulator by 4 bits.
5
SIGNEXP Expected Accumulator Sign.
This bit sets the expected sign of the accumulator after an operation. A signed operation
that does not match the SIGNEXP bit will set the SCHANGE bit.
This bit can only be used with signed arithmetic (SIGNEDEN = 1).
0: Set the expected sign to zero.
1: Set the expected sign to one.
4 SIGNEDEN Signed Mode Enable.
0: MAC operations use unsigned arithmetic.
1: MAC operations use signed arithmetic.
3
MAC0BC B DMA Data Source Selection.
This bit controls the source of data for the MAC0 B register when operating in DMA
mode. This bit is ignored when the MAC0 module operates in MCU mode.
0: Each MAC0 operation will request the DMA fetch data from XRAM for the MAC0 B
register.
1: Each MAC0 operation will use existing data in MAC0 B register.
2 BPOSTINC B Post-Increment Enable.
This bit controls whether the MAC0 B register value is incremented after a MAC0 opera-
tion. This bit can be used in both MCU and DMA modes.
0: Do not change the MAC0 B register after a MAC0 operation.
1: Increment the MAC0 B register after a MAC0 operation.
218
Rev 1.0