C8051F970-A-GM Datasheet, PDF (89/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 13.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
3
2
1
0
Name EI2C0 ECSEOS ECSDC ECSCPT EMAC0 ERTC0F EMAT Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = ALL; SFR Address: 0xE7
Table 13.6. EIE2 Register Bit Descriptions
Bit
Name
Function
7
EI2C0 I2C0 Slave Interrupt Enable.
0: Disable I2C0 Slave event interrupt.
1: Enable interrupt requests generated by the I2C0 Slave.
6
ECSEOS Capacitive Sense End of Scan Interrupt Enable.
This bit sets the masking of the Capacitive Sense End of Scan interrupt.
0: Disable Capacitive Sense End of Scan interrupt.
1: Enable interrupt requests generated by the Capacitive Sense End of Scan.
5
ECSDC Capacitive Sense Digital Comparator Interrupt Enable.
This bit sets the masking of the Capacitive Sense Digital Comparator interrupt.
0: Disable Capacitive Sense Digital Comparator interrupt.
1: Enable interrupt requests generated by the Capacitive Sense Digital Comparator.
4
ECSCPT Capacitive Sense Conversion Complete Interrupt Enable.
This bit sets the masking of the Capacitive Sense Conversion Complete interrupt.
0: Disable Capacitive Sense Conversion Complete interrupt.
1: Enable interrupt requests generated by CS0INT.
3
EMAC0 MAC0 Interrupt Enable.
0: Disable MAC0 event interrupt.
1: Enable interrupt requests generated by MAC0.
2
ERTC0F RTC Oscillator Fail Interrupt Enable.
This bit sets the masking of the RTC Alarm interrupt.
0: Disable RTC Alarm interrupts.
1: Enable interrupt requests generated by the RTC Alarm.
1
EMAT Port Match Interrupts Enable.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
0
Reserved Must write reset value.
Rev 1.0
89