C8051F970-A-GM Datasheet, PDF (344/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
All transactions are initiated by a master, with one or more addressed slave devices as the target. The master
generates the START condition and then transmits the slave address and direction bit. If the transaction is a
WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK
from the slave at the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from
the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to
terminate the transaction and free the bus. Figure 29.3 illustrates a typical SMBus transaction.
SCL
SDA
SLA6
SLA5-0
R/W
D7
D6-0
START
Slave Address + R/W
ACK
Data Byte
NACK
STOP
Figure 29.3. SMBus Transaction
29.3.1. Transmitter vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or data byte to
another device on the bus. A device is a “receiver” when an address or data byte is being sent to it from another
device on the bus. The transmitter controls the SDA line during the address or data byte. After each byte of
address or data information is sent by the transmitter, the receiver sends an ACK or NACK bit during the ACK
phase of the transfer, during which time the receiver controls the SDA line.
29.3.2. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and
SDA lines remain high for a specified time (see Section “29.3.5. SCL High (SMBus Free) Timeout” on page 346). In
the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed
to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while
the other transmits a LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the
HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without
interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration
scheme is non-destructive: one device always wins, and no data is lost.
29.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed
capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave
devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock
low period, effectively decreasing the serial clock frequency.
29.3.4. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the
master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol
specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a
“timeout” condition. Devices that have detected the timeout condition must reset the communication no later than
10 ms after detecting the timeout condition.
For the SMBus0 interface, Timer 3 is used to implement SCL low timeouts. The SCL low timeout feature is enabled
by setting the SMB0TOE bit in SMB0CF. The associated timer is forced to reload when SCL is high, and allowed to
count when SCL is low. With the associated timer enabled and configured to overflow after 25 ms (and SMB0TOE
set), the timer interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an
SCL low timeout.
Rev 1.0
345