C8051F970-A-GM Datasheet, PDF (82/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
13.2. Interrupt Control Registers
Register 13.1. IE: Interrupt Enable
Bit
7
6
5
4
3
2
1
0
Name
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = ALL; SFR Address: 0xA8 (bit-addressable)
Table 13.2. IE Register Bit Descriptions
Bit
Name
Function
7
EA
All Interrupts Enable.
Globally enables/disables all interrupts and overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6
ESPI0 SPI0 Interrupt Enable.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
5
ET2
Timer 2 Interrupt Enable.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4
ES0
UART0 Interrupt Enable.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
3
ET1
Timer 1 Interrupt Enable.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2
EX1
External Interrupt 1 Enable.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
1
ET0
Timer 0 Interrupt Enable.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
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