C8051F970-A-GM Datasheet, PDF (213/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
22.12. MAC0 Registers
Register 22.1. MAC0STA: MAC0 Status
Bit
7
6
5
4
Name Reserved MACINT SCHANGE ACCRDY
Type
RW
RW
RW
RW
Reset
0
0
0
0
SFR Page = 0xF; SFR Address: 0xCF
3
HOVF
RW
0
2
ZEROF
RW
0
1
SOVF
RW
0
0
BUSY
RW
0
Bit
Name
Function
7
Reserved Must write reset value.
6
MACINT Interrupt Flag.
This flag is set when at least one of the following conditions are met:
- Hardware overflow bit (HOVF) is set.
- Soft overflow bit (SOVF) is set AND the SOVFIEN bit is set.
- The ACCRDY bit is set when the MAC operates in MCU mode.
Firmware must clear this bit.
5
SCHANGE Sign Change Event.
Hardware sets this bit when operating in signed mode (SIGNEDEN = 1) and the sign bit
of the MAC0 accumulator result is opposite of the expected sign (SIGNEXP) bit.
Firmware must clear this bit. This bit also clears automatically if firmware clears the accu-
mulator by setting the CLRACC bit in the MAC0CF0 register.
4
ACCRDY ACC Ready Status Flag.
This bit is set only when the MAC operates in MCU mode and a MAC operation com-
pletes. This bit must be cleared by firmware.
3
HOVF Hard Overflow Flag.
This bit is set to 1 when the a MAC operation results in a hardware overflow.
Hardware overflow for a signed operation (SIGNEDEN = 1) occurs when a MAC opera-
tion causes MAC0OVF to change from 0x7F to 0x80 or 0x80 to 0x7F.
Hardware overflow for an unsigned operation (SIGNEDEN = 0) occurs when a MAC
operation causes MAC0OVF to change from 0xFF to 0x00.
Firmware must clear this bit. This bit also clears automatically if firmware clears the accu-
mulator by setting the CLRACC bit in the MAC0CF0 register.
2
ZEROF Zero Flag.
This bit is set to 1 if a MAC operation results in a MAC accumulator value of zero.
Firmware must clear this bit. This bit also clears automatically if firmware clears the accu-
mulator by setting the CLRACC bit in the MAC0CF0 register.
214
Rev 1.0